The invention relates to a circuit for selectively generating an output signal from one or more clock signals.
Digital microelectronic circuits require clock signals for their operation, which signals predetermine the clock rates. Under circumstances, the situation may occur that the logic circuit is to be alternately operated at different clock rates which are derived from different clock signals. For example, it may be necessary to be able to operate the central processor (CPU) of a microcomputer optionally with a fast and a slow clock in order that it can adapt to slower peripheral apparatus, if any. Also in smart card controllers, the sources for the chip clock may be different dependent on their application. For example, an external clock may be supplied via a pin of the smart card or it may serve as an internal source for an on-chip oscillator.
When switching between different system clocks, it is to be taken into account that no undefined states or voltage pulses (glitches) occur during switching. Circuits allowing a switch-over between a plurality of clock signals or between two different clock signals under these circumstances are described in, for example, U.S. Pat. Nos. 5,483,185, 5,604,452 and 5,790,609. In the known circuits, the predetermined clock signals are applied to a multiplexer whose output supplies one of the clock signals, which can be selected via a control input of the multiplexer, as an output signal. The switch-over between two clock signals is controlled by a control means in such a way that no undefined signal states can occur at the output. To this end, the output signal is maintained during a switching process at a level which corresponds to a logic high state. Starting from this state, the output signal subsequently proceeds at the newly selected clock. However, by waiting for a high state, a proportionally long period of time is lost in the switching process when the output signal is just in a logic low state at the start of the switching process. In the case of frequent switching processes, noticeable delays may therefore occur in the circuit. Moreover, known circuits have in common that the control therein is performed by one of the external clock signals. When this clock signal is disturbed or stopped, the function of the circuit will be interrupted.
Based on this recognition, it is an object of the invention to provide a circuit for selectively generating an output signal from a plurality of input clock signals, allowing a fast and interference-free switching between the clock signals. Simultaneously, the circuit should be failsafe and preferably realized in a CMOS technique by simple means.
This object is solved by a circuit as defined in claim 1. Advantageous embodiments are defined in the dependent claims.
The circuit for selectively generating an output signal from one or more input clock signals comprises the following elements:
A) a multiplexer having a plurality of inputs for the input clock signals, a control input for selecting one of the input clock signals, and a multiplexer output for supplying the selected input clock signal;
B) a signal latch arranged between the multiplexer output and the output of the circuit, in which the connection line to the multiplexer output comprises a switch;
C) a switching logic with a control input for an external clock selection signal, signal inputs for the signal of the multiplexer output and the output signal of the circuit, a clock input for a logic clock signal, and a control output which is connected to the control input of the multiplexer, and a disable signal output which is connected to the switch.
The switching logic is adapted in such a way that it opens the switch when the signal at its control input changes, subsequently passes on the changed signal from its control input to its control output and thereby to the multiplexer, and closes the switch again when the output signal at the multiplexer output has changed at least once since the switch was opened, and is equal to the output signal of the circuit stored in the signal latch.
The circuit described allows selective switching of one of the input clock signals to the output signal, in which no undefined states or interference voltages occur in the output signal during switching between two different input clock signals. This is achieved in that the multiplexer output is connected to the output of the circuit via a signal latch and that the connection between the multiplexer and the signal latch can be interrupted by a switch. Such an interruption is performed prior to switching between two input clock signals so that, during switching, the output of the circuit is only connected to the signal latch and, consequently, maintains the current signal level (high or low) constant and free from interference. Only when the switching process is ended and a stable signal, whose level corresponds to the level of the signal in the signal latch, is present at the multiplexer output, the switch is closed again so that the output signal now follows the newly selected input clock signal.
During switching, the circuit ascertains that the level of the output signal present at the start of the switching process is maintained for at least the shortest clock period occurring among the input clock signals. In this way, interference of the connected logic circuit by a clock signal which is too short is excluded. Said effect is achieved in that the control first waits for at least a switch of the signal at the multiplexer output before it closes the switch again and thereby connects the multiplexer output to the signal latch again. It is thus ensured that the current latch state lasts at least one full clock length of the new signal.
The proposed circuit preferably comprises at least a clock generator which is coupled to the clock input of the switching logic so as to make a logic clock signal available. Because of its own clock generator, the circuit will be independent of the external clock signals so that it can also continue to operate in the case of failure or interference. Furthermore, its own clock can ensure that the switching logic operates quickly enough to react substantially without delay to the input clock signals.
The switching logic of the proposed circuit may particularly be constituted as a state machine whose states and state transitions are implemented in such a way that it performs the following steps:
a) waiting for a change of the clock selection signal at the control input;
b) supplying a disable signal at the disable signal output for opening the switch when the clock selection signal at the control input has changed;
c) passing on the clock selection signal from the control input to the control output which leads to the control input of the multiplexer;
d) waiting for a change of the signal at the multiplexer output;
e) if the changed signal at the multiplexer output is not equal to the output signal of the circuit, waiting again for a change of the signal at the multiplexer output;
f) eliminating the disable signal at the disable signal output so as to close the switch, and returning to step a).
Such a state machine has the advantage that its function can be defined in standardized circuit description languages which allow a simple and automatic conversion of the function predetermined in logic steps in a concrete circuit.
The circuit according to the invention is preferably realized in a CMOS technique. This is a known and reliable technique which allows integration of the circuit on conventional microchips. Particularly, the circuit may be used in connection with a smart card chip. In smart cards, the situation often occurs that the chip is to be optionally controlled with an externally supplied or internally generated clock and that the security requirements imposed on the function of a smart card are very stringent. The occurrence of an undefined signal state in the output signal or even a reset of the chip during a switching process are to be avoided in any case.